Method of manufacturing a semiconductor device including a mosfet with nitride sidewalls

ABSTRACT

A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a semiconductor device and to a methodfor manufacturing the same. In particular, the present invention relatesto a MOSFET which has side wall structure and to a method formanufacturing the same.

[0003] This is a counterpart of, and claims priority to, Japanese PatentApplication No. 2000-1025, filed on Jan. 17, 2000, the contents of whichare incorporated herein by reference.

[0004] 2. Description of the Related Art

[0005] A Self-Aligned Contact (SAC) method is an important techniqueused in fabricating semiconductor devices. This technology is describedin the article entitled “A Process Technology for 1 Giga-Bit DRAM” IEDMTech. Dig., pp907-910, 1995.

[0006] SiN is generally used as sidewalls of a gate electrode in the SACprocess. This is because the etching rate of SiN is different from thatof silicon-oxide, and therefore SiN sidewalls are used as a stopper inetching on an intermediate oxide layer.

[0007]FIG. 23 is a schematic diagram of a MOSFET 800 manufactured usingan SAC process.

[0008] A gate oxide layer 824 having a constant thickness is formed on asilicon substrate 802. A gate electrode 816 is formed on the gate oxidelayer 824. A SiN cap layer 820 is formed on the gate electrode 816. SiNsidewalls 822, which cover the side surfaces of the gate electrode 816,are formed on the gate oxide layer 824.

[0009] A heat treatment is generally performed in manufacturing of theMOSFET 800 after the formation of sidewalls. In case of SiN sidewalls,hydrogen and nitrogen may be diffused into the silicon substrate 802through the gate oxide layer 824 during the heat treatment. Therefore,MOSFETs which have SiN sidewalls are less reliable due to resultanthot-carrier degradation than MOSFETs which have sidewalls of siliconoxide. These problems are pointed out and discussed in the articleentitled Enhancement of Hot-Carrier Induced Degradation under Low GateVoltage Stress due to Hydrogen for NMOSFETs with SiN films” S.Tokitoh etal. IRPS, pp307-311, 1997 and “Hot-carrier Degradation Mechanism andPromising Device Design of nMOSFETs with Niteride Sidewall Spacer”Y.Yamasugi et al. IRPS, pp 184-188, 1998.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide a reliablesemiconductor device, and to provide a method for manufacturing thesame.

[0011] According to one aspect of the present invention, for achievingthe above object, A semiconductor device includes a semiconductorsubstrate, a silicon oxide layer formed over a surface of thesemiconductor substrate, a gate electrode formed over a first portion ofthe silicon oxide layer, and a side wall structure formed over a secondportion of the silicon oxide layer and adjacent the gate electrode,wherein a thickness of the second portion of the silicon oxide layer isgreater than a thickness of the first portion of the silicon oxidelayer.

[0012] According to another aspect of the present invention, forachieving the above object, A method for manufacturing a semiconductordevice includes forming a gate oxide layer on a surface of asemiconductor substrate, forming a gate electrode and over a firstportion of the gate oxide layer, forming a cap layer over the gateelectrode, expanding a thickness of a second portion of the gate oxidelayer other than the first portion located under the gate electrode,forming a side wall structure on the second portion of the gate oxidelayer and adjacent the gate electrode, forming intermediate insulatinglayer over the cap layer and the side wall structure, and forming acontact hole in the intermediate insulating layer using a Self AlignedContact process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter that is regardedas the invention, the invention, along with the objects, features, andadvantages thereof, will be better understood from the followingdescription taken in conjunction with the attached drawings, in which:

[0014]FIG. 1 is a cross sectional view showing a semiconductor deviceaccording to a first preferred embodiment.

[0015]FIG. 2 is a flow chart of a method for manufacturing thesemiconductor device of first embodiment.

[0016]FIG. 3 is a cross sectional view showing the method formanufacturing the semiconductor device of the first embodiment.

[0017]FIG. 4 is a cross sectional view showing a semiconductor deviceaccording to a second preferred embodiment.

[0018]FIG. 5 is a flow chart of a method for manufacturing thesemiconductor device of the second embodiment.

[0019]FIG. 6 is a cross sectional view showing the method formanufacturing the semiconductor device of the second embodiment.

[0020]FIG. 7 is a cross sectional view showing a semiconductor deviceaccording to a third preferred embodiment.

[0021]FIG. 8 is a flow chart of a method for manufacturing thesemiconductor device of the third embodiment.

[0022]FIG. 9 is a cross sectional view showing the method formanufacturing the semiconductor device of the third embodiment.

[0023]FIG. 10 is a cross sectional view showing a semiconductor deviceaccording to a fourth preferred embodiment.

[0024]FIG. 11 is a flow chart of a method for manufacturing thesemiconductor device of the fourth embodiment.

[0025]FIG. 12 is a cross sectional view showing the method formanufacturing the semiconductor device of the fourth embodiment.

[0026]FIG. 13 is a cross sectional view showing a semiconductor deviceaccording to a fifth preferred embodiment.

[0027]FIG. 14 is a flow chart of a method for manufacturing thesemiconductor device of the fifth embodiment.

[0028]FIG. 15 is a cross sectional view showing the method formanufacturing the semiconductor device of the fifth embodiment.

[0029]FIG. 16 is a cross sectional view showing a semiconductor deviceaccording to a sixth preferred embodiment.

[0030]FIG. 17 is a flow chart of a method for manufacturing thesemiconductor device of the sixth embodiment.

[0031]FIG. 18 is a cross sectional view showing the method formanufacturing the semiconductor device of the sixth embodiment.

[0032]FIG. 19 is a cross sectional view showing a semiconductor deviceaccording to a seventh preferred embodiment.

[0033]FIG. 20 is a flow chart of a method for manufacturing thesemiconductor device of the seventh embodiment.

[0034]FIG. 21 is a cross sectional view showing the method formanufacturing the semiconductor device of the seventh embodiment.

[0035]FIG. 22 shows the impurity concentration of the LDD regions of theseventh embodiment

[0036]FIG. 23 shows a schematic diagram of the MOSFET 800 manufacturedby using a Self Aligned Contact process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037]FIG. 1 is a cross sectional view showing a semiconductor deviceaccording to a first preferred embodiment of this invention.

[0038] The semiconductor device 100 of this embodiment has a siliconsubstrate 102, an intermediate insulating layer 104, and a MOSFET 110.The MOSFET 110 is formed on the silicon substrate 102. The intermediateinsulating layer 104 is formed on the silicon substrate 102 and MOSFET110. The intermediate insulating layer 104 is made of silicon oxide.

[0039] MOSFET 110 has a source region 112, a drain region 114, a gateelectrode 116, and a channel region 118. The MOSFET 110 of thisembodiment has a LDD structure as shown by 112 a, 114 a. The sourceregion 112, the drain region 114 and the channel region 118 are formedin the semiconductor substrate 102. The gate electrode 116 is formedover the semiconductor substrate 102. The channel region 118 is formedbetween the source region 112 and the drain region 114, and under thegate electrode 116. For example, the N channel MOSFET (110) includes a Ptype substrate (102) into which two heavily doped N regions (112,114)and two lightly doped regions (112 a,114 a) have been diffused.

[0040] MOSFET 110 has a cap layer 120 and sidewall structure 122. Thecap layer 120 is formed on the gate electrode 116. Sidewall structure122 are formed over the silicon substrate 102. The sidewalls 122 coverboth sides of the gate electrode 116. A material which is different fromthe intermediate insulating layer 104 is used as the cap layer 120 andsidewalls 122. The cap layer 120 and sidewalls 122 are made of SiN inthis embodiment.

[0041] The MOSFET 110 has a gate oxide layer 124 and diffusion deterrentlayers 126. The gate oxide layer 124 and a diffusion deterrent layer 126are formed on the surface of the silicon substrate 102. The gate oxidelayer 124 is formed under the gate electrode 116. The diffusiondeterrent layers 126 are formed under the sidewalls 122. These diffusiondeterrent layers 126 prevent hydrogen and nitrogen in the sidewalls 122from diffusing into the silicon substrate 102. The gate oxide layer 124has a thickness of about 10 nm (100 Å). The diffusion deterrent layers126 are preferably twice the thickness against of the gate oxide layer124. The gate oxide layer 124 and the diffusion deterrent layers 126 aremade of silicon oxide. Since the thicknesses of the diffusion deterrentlayers 126 are greater than the gate oxide layer 124, hydrogen andnitrogen in the sidewalls do not diffuse into the silicon substrate 102.

[0042] The semiconductor device also has first contact holes 106 a,first interconnections 108 a, a second contact hole 106 b, and a secondinterconnection 108 b.

[0043] The first contact holes 106 a are formed using a SAC process. SiNsidewalls 122 are used as a stopper in etching on the intermediate oxidelayer 104. The first interconnections 108 a are respectively connectedto the drain region 114 and the source region 112. The secondinterconnection 108 b is connected to the gate electrode 116.

[0044] For example, in a semiconductor memory-cell, the source region112 is connected to a bit line, and the drain region 114 is connected toa storage capacitor, through first interconnections 108 a. The gateelectrode 116 is connected to a word line through the secondinterconnection 108 b.

[0045] The MOSFET 110 of this embodiment has a silicon oxide layer 126under the sidewalls, and this silicon oxide layer 126 is thicker thanthe silicon oxide layer 124 under the gate electrode 116. The siliconoxide layer 126 has a thickness to prevent the diffusion of hydrogen andnitrogen. Therefore, the silicon oxide layer 126 works as diffusiondeterrent layer. The thickness of the diffusion deterrent layer 126depends on the width of sidewalls 122. There is an effect if thethickness of the silicon oxide layer 126 is 50% greater than thethickness of the silicon oxide layer 124. However, it is desirable thatthe diffusion deterrent layer 126 be at least twice the thickness of thegate oxide layer 124.

[0046]FIG. 2 is a flow chart of a method for manufacturing thesemiconductor device of this embodiment, and FIG. 3 is a cross sectionalview showing the method for manufacturing the same. The method formanufacturing the semiconductor device of this embodiment is describedbelow.

[0047] The gate oxide layer 124 is formed on the surface of thesemiconductor substrate 102 using a thermal oxidation. (Step 21) Thisgate oxide layer 124 has a thickness of about 10 nm.

[0048] The gate electrode material 116 and the cap layer material 120are formed on the gate oxide layer 124 as seen in FIG. 3(a). Alithography method and an anisotropic etching technique, such as a RIEmethod, are employed to etch the gate electrode material 116 and the caplayer material 120. The gate electrode 116 and the cap layer are formedas seen in FIG. 3(b). (Step 22)

[0049] Ion implantation for forming the LDD region 112 a and 114 a isperformed by using the cap layer 120 as the mask. This implantationmakes lightly doped regions 112 a and 114 a. (Step 23)

[0050] A silicon oxide layer 126 is formed on the gate oxide layer 124using CVD. As the gate electrode 116 and the cap layer 120 are used as amask, this silicon oxide layer 126 is deposited on the gate oxide layer124 other than the portion under the gate electrode 116 (as shown inFIG. 3(c)). Therefore, a thickness of the gate oxide layer other thanthe portion under the gate electrode layer is increased. This siliconoxide layer 126 works as the diffusion deterrent layer 126. (Step 24)The oxide layer 126 is deposited at about 10 nm on the gate oxide layerbeside the gate electrode 126, therefore the diffusion deterrent layer126 has a thickness of about 20 nm.

[0051] An SiN sidewall layer, having a thickness of from 100 nm to 200nm, is formed over the semiconductor substrate using LP-CVD. Ananisotropic etching technique, such as a RIE method, is employed to etchthe SiN sidewall layer, so that SiN sidewalls are formed. (Step 25)

[0052] An ion implantation for forming the source region 112 and thedrain region 114 is performed by using the cap layer 120 and sidewalls122 as a mask. An annealing is performed after the ion implantation.This annealing diffuses implanted ions and forms the source region 112and the drain region 114 as shown in FIG. 3(d). (Step 26)

[0053] The intermediate insulating layer 104 is formed over thesemiconductor substrate 102. (Step 27) The intermediate insulating layer104 is made of a material which is different from the material of thecap layer 120 and the side walls 122. The intermediate insulating layer104 is made of silicon oxide in this embodiment.

[0054] The first contact holes 106 a are formed using a SAC process.(Step 28) The intermediate insulating layer 104 is etched using anetchant which has a smaller etching rate for SiN than for silicon-oxide.SiN sidewalls are used as a stopper. The intermediate layer 104 and thesilicon oxide 126 over the source region and drain region are etched inthis step.

[0055] The interconnections 108 a are formed in the contact holes 106 a.The second contact hole and the second interconnection are formed afterthe first interconnections are formed.

[0056] In this embodiment, the diffusion deterrent layers 126 preventhydrogen and nitrogen in the sidewalls from diffusing into the siliconsubstrate 102 during annealing. Therefore, interface traps, which arerelated to hot carrier, are reduced near the surface of thesemiconductor substrate, this improving the reliability of the MOSFET110.

[0057] The diffusion deterrent layer 126 is formed using CVD in thisembodiment. Therefore, the thickness of the diffusion deterrent layer126 is controlled precisely, and characteristics of the MOSFET areeasily controlled.

[0058]FIG. 4 is a cross sectional view showing a semiconductor deviceaccording to a second preferred embodiment of this invention.

[0059] The semiconductor device 200 has a MOSFET 210. The MOSFET 210 hasa gate electrode 216. The gate electrode 216 of this embodiment hasoxide wall layers 216 a on its side surfaces.

[0060] The MOSFET 210 has a diffusion deterrent layer 226 on the surfaceof the silicon substrate 202. The other parts of the semiconductordevice of this embodiment are the same as those in the first embodiment.

[0061]FIG. 5 is a flow chart of a method for manufacturing thesemiconductor device of this embodiment, and FIG. 6 is a cross sectionalview showing the method for manufacturing the same. The method formanufacturing the semiconductor device of this embodiment is describedbelow.

[0062] The gate oxide layer 224 is formed on the surface of thesemiconductor substrate 202 using thermal oxidation. This gate oxidelayer 224 has a thickness of about 10 nm. (Step 51)

[0063] The gate electrode material 216 and the cap layer material 220are formed on the gate oxide layer 224. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 216 and the cap layer material 220. Thegate electrode 216 and the cap layer are formed as seen in FIG. 6(a).(Step 52)

[0064] Ion implantation for forming the LDD region 212 a and 214 a isperformed by using the cap layer 220 as the mask. This implantationmakes lightly doped regions 212 a and 214 a. (Step 53)

[0065] A silicon oxide layer 226 is formed on the gate oxide layer 224using a thermal oxidation. The thermal oxidation of this embodiment isperformed at a temperature of 850° C. and in an oxygen atmosphere. Thisthermal oxidation thickens the gate oxide layer other than at theportion thereof under the gate electrode 216. Oxide wall layers 216 a ofthe gate electrode 216 are also formed in this thermal oxidation as seenin FIG. 6(b). This silicon oxide layer 226 works as the diffusiondeterrent layer 226. The oxide layer 226 has a thickness of about 20 nm.(Step 54)

[0066] A SiN sidewall layer, having a thickness from 100 nm to 200 nm,is formed on the semiconductor substrate using LP-CVD. An anisotropicetching technique, such as a RIE method, is employed to etch the SiNsidewall layer, so that SiN sidewalls are formed as seen in FIG. 6(c).(Step 55) Subsequent steps are the same as those in the firstembodiment.(Step 56-58)

[0067] In this embodiment, the diffusion deterrent layer 226 preventhydrogen and nitrogen in the sidewalls from diffusing into the siliconsubstrate 202 during annealing. Therefore, interface traps, which arerelated to hot carrier, are reduced near the surface of thesemiconductor substrate, and the reliability of the MOSFET is improved.

[0068] The diffusion deterrent layer 226 is formed using thermaloxidation in this embodiment. A thin oxide layer between the sidewallsand the cap layer as shown in the first embodiment is not formed.Therefore, the alignment in the SAC process becomes more flexible.

[0069]FIG. 7 is a cross sectional view showing a semiconductor deviceaccording to a third preferred embodiment of this invention.

[0070] The semiconductor device 300 has a structure which is similar tothat of the second embodiment. In third embodiment, the silicon oxidelayer covering the side surfaces of the gate electrode is not formed.

[0071]FIG. 8 is a flow chart of a method for manufacturing thesemiconductor device of this embodiment, and FIG. 9 is a cross sectionalview showing the method for manufacturing the same. The method formanufacturing the semiconductor device of this embodiment is describedbelow.

[0072] The gate oxide layer 324 is formed on the surface of thesemiconductor substrate 302 using a thermal oxidation. This gate oxidelayer 324 has a thickness of about 10 nm. (Step 81)

[0073] The gate electrode material 316 and the cap layer material 320are formed on the gate oxide layer 324. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 316 and the cap layer material 320. Thegate electrode 316 and the cap layer are formed as seen in FIG. 9(a).(Step 82)

[0074] Ion implantation for forming the LDD regions 312 a and 314 a isperformed using the cap layer 320 as a mask. This implantation makeslightly doped regions 312 a and 314 a. (Step 83)

[0075] A SiN sidewall layer, having a thickness from 100 nm to 200 nm,is formed on the semiconductor substrate using LP-CVD. An anisotropicetching technique, such as a RIE method, is employed to etch SiNsidewall layer, so that SiN sidewalls are formed as seen in FIG. 9(b).(Step 84)

[0076] A silicon oxide layer 326 is formed on the gate oxide layer 324using a thermal oxidation as seen in FIG. 9(c). The thermal oxidation ofthis embodiment is performed at a temperature of 850° C. and in anoxygen atmosphere. Thickening begins from the edge portion 322 a underthe side walls, and it expand into the portion near the gate electrode326. The time of this oxidation is controlled to expand the thickness ofthe gate oxide layer other than at the portion lying under the gateelectrode 316. This silicon oxide layer 326 works as the diffusiondeterrent layer 326. The oxide layer 326 has a thickness of about 20 nm.(Step 85) Subsequent steps are the same as those in the secondembodiment. (Step 86-88)

[0077] In this embodiment, the diffusion deterrent layer 326 preventshydrogen and nitrogen in the sidewalls from diffusing into the siliconsubstrate 102 during annealing. Therefore, interface traps, which arerelated to hot carrier, are reduced near the surface of thesemiconductor substrate, and the reliability of the MOSFET is improved.

[0078] The thermal oxidation is performed after the formation ofsidewalls in this invention. This thermal oxidation reduces hydrogen inthe oxide layer 324 under the sidewalls. Also an oxide layer on the sidesurface of the gate electrode is not formed in this embodiment.Therefore, a variation of the gate electrode resistance is prevented.

[0079]FIG. 10 is a cross sectional view showing a semiconductor deviceaccording to a fourth preferred embodiment of this invention.

[0080] The semiconductor device 400 has the same structure as the thirdembodiment.

[0081]FIG. 11 is a flow chart of the method for manufacturing asemiconductor device of this embodiment, and FIG. 12 is a crosssectional view showing the method for manufacturing the same. The methodfor manufacturing the semiconductor device of this embodiment isdescribed below.

[0082] The gate oxide layer 424 is formed on the surface of thesemiconductor substrate 402 by using thermal oxidation. This gate oxidelayer 424 has a thickness of about 10 nm. (Step S111)

[0083] The gate electrode material 416 and the cap layer material 420are formed on the gate oxide layer 424. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 416 and the cap layer material 420. Thegate electrode 416 and the cap layer are thereby formed. (Step S112)

[0084] Ion implantation for forming the LDD region 412 a and 414 a isperformed by using the cap layer 420 as the mask. This implantationmakes lightly doped regions 412 a and 414 a. (Step S113)

[0085] A SiN sidewall layer, having a thickness from 100 nm to 200 nm,is formed on the semiconductor substrate using LP-CVD. An anisotropicetching technique, such as a RIE method, is employed to etch the SiNsidewall layer so that SiN sidewalls 422 are formed. (Step S114)

[0086] Ion implantation for forming the source region 412 and drainregion 414 is performed using the cap layer 420 and sidewalls 422 as amask. An annealing is performed after the ion implantation. Thisannealing diffuses implanted ion and forms source region 412 and drainregion 414. (FIG. 12(a), Step S115)

[0087] The intermediate insulating layer 404 is formed on thesemiconductor substrate 402. The intermediate insulating layer 404 ismade of BPSG in this embodiment. (FIG. 12(b), Step S116)

[0088] A silicon oxide layer 426 is formed on the gate oxide layer 424using thermal oxidation. The thermal oxidation of this embodiment isperformed at a temperature of over 850° C. and in an oxygen atmosphere.Thickening begins from the edge portion 422 a of the side walls, andexpands into the portion near the gate electrode 416. The time of thisoxidation is controlled to expand the thickness of the gate oxide layerother than at the portion lying under the gate electrode 416. Thissilicon oxide layer 426 works as the diffusion deterrent layer. Theoxide layer 426 has a thickness of about 20 nm. Subsequent steps are thesame as those in the third embodiment. (FIG. 12(c), Step S118)

[0089] In this embodiment, the thermal oxidation is performed after theformation of the sidewalls and source/drain regions. Hydrogen andnitrogen in the sidewalls are diffused into the surface of siliconsubstrate during annealing. However, the thermal oxidation oxidizes thesurface of silicon substrate. Therefore, interface traps, which arerelated to hot carrier, are reduced, and reliability is improved. Anoxide layer on the side surface of the gate electrode is not formed inthis embodiment. Therefore, the variation in resistance of the gateelectrode is prevented.

[0090] The surface of the intermediate insulating layer 404 is flattenedduring thermal oxidation because the intermediate insulating layer ismade of BPSG. Therefore, manufacturing is simplified in this embodiment.

[0091]FIG. 13 is a schematic diagram of this embodiment. As shown inFIG. 13, the semiconductor device of this embodiment has a structurewhich is similar to that of the prior art. In this embodiment, however,the method for manufacturing the semiconductor device is different fromthe prior art.

[0092]FIG. 14 is a flow chart of the method for manufacturing thesemiconductor device of this embodiment, and FIG. 15 is a crosssectional view showing the method for manufacturing the same. The methodfor manufacturing the semiconductor device of this invention isdescribed below.

[0093] The gate oxide layer 524 is formed on the surface of thesemiconductor substrate 502 by using thermal oxidation. This gate oxidelayer 524 has a thickness of about 10 nm. (Step S141)

[0094] The gate electrode material 516 and the cap layer material 520are formed on the gate oxide layer 524. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 516 and the cap layer material 520. Thegate electrode 516 and the cap layer are thereby formed as seen in FIG.15(a). (Step S142)

[0095] Ion implantation for forming the LDD region 512 a and 514 a isperformed using the cap layer 520 as a mask. This implantation makeslightly doped regions 512 a and 514 a. (Step S143)

[0096] A SiN sidewall layer, having a thickness from 100 nm to 200 nm,is formed on the semiconductor substrate using LP-CVD. The formation ofthe SiN sidewall layer is performed at a temperature of over 850° C.Experiments os the inventor have shwon that high temperature formationof the SiN sidewall reduces the hydrogen that diffuses into thesemiconductor substrate. An anisotropic etching technique, such as a RIEmethod, is employed to etch the SiN sidewall layer, so that SiNsidewalls are formed. (FIG. 15(b), Step S144)

[0097] Ion implantation for forming the source region 512 and drainregion 514 is performed using the cap layer 520 and sidewalls 522 as amask. An annealing is performed after the ion implantation. Thisannealing diffuses implanted ions and forms source region 512 and drainregion 514. (FIG. 15(c), Step S145)

[0098] The intermediate insulating layer 504 is formed on thesemiconductor substrate 502. The intermediate insulating layer 504 ismade of a material which is different from the material of the cap layer520 and the side walls 522. The intermediate insulating layer 104 ismade of silicon oxide in this embodiment. (Step S146)

[0099] The first contact holes 506 a are formed using a SAC process. Theintermediate insulating layer 504 is etched using an etchant which has asmaller etching rate for SiN than for silicon-oxide. Therefore, the SiNsidewalls are used as a stopper. The intermediate layer 504 and thesilicon oxide 524 over the source region and drain region are etched inthis step. (Step S147) Subsequent steps are the same as those of otherembodiments.

[0100] In this embodiment, high temperature formation of SiN sidewallsreduces the hydrogen and nitrogen that diffuses into the siliconsubstrate 502. For example, amount of hydrogen which diffuses into thesemiconductor substrate when the sidewalls are made at 850° C. is aboutone-third of that made at 780° C.

[0101] Therefore, interface traps, which are related to hot carrier, arereduced near the surface of the semiconductor substrate, and thereliability of the MOSFET is improved.

[0102]FIG. 16 is a schematic diagram of this embodiment. As shown inFIG. 16, The SiN sidewalls of this embodiment have two layers.

[0103]FIG. 17 is a flow chart of a method for manufacturing thesemiconductor device of this embodiment, and FIG. 18 is a crosssectional view showing the method for manufacturing the same. The methodfor manufacturing the semiconductor device of this embodiment isdescribed below.

[0104] The gate oxide layer 624 is formed on the surface of thesemiconductor substrate 602 by using thermal oxidation. This gate oxidelayer 624 has a thickness of about 10 nm. (Step S171)

[0105] The gate electrode material 616 and the cap layer material 620are formed on the gate oxide layer 624. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 616 and the cap layer material 620. Thegate electrode 616 and the cap layer are thereby formed. (Step S172)

[0106] Ion implantation for forming the LDD region 612 a and 614 a isperformed by using the cap layer 620 as the mask. This implantationmakes lightly doped regions 612 a and 614 a. (Step S173)

[0107] A first SiN sidewall layer 622 a, having a thickness from 20 nmto 40 nm, is formed on the semiconductor substrate using LP-CVD. Theformation of the first SiN sidewall layer is performed at a temperatureexceeding 850° C. as shown in FIG. 18(a). (Step S174) The hightemperature formation of the SiN sidewall reduces the hydrogen thatdiffuses into the semiconductor substrate. Then, a second SiN sidewalllayer 622 b, having a thickness from 80 nm to 160 nm, is formed on thefirst sidewall layer using LP-CVD.(FIG. 18(b) The formation of thesecond SiN sidewall is performed at a temperature of about 780° C. Ananisotropic etching technique, such as a RIE method, is employed to etchfirst and second SiN sidewall layers, so that SiN sidewalls 622 areformed as shown in FIG. 18(c). (Step S175)

[0108] Ion implantation for forming the source region 612 and drainregion 614 is performed by using the cap layer 620 and sidewalls 622 asa mask. An annealing is performed after the ion implantation. Thisannealing diffuses implanted ions and forms source region 612 and drainregion 614. (Step S176)

[0109] The intermediate insulating layer 604 is formed over thesemiconductor substrate 602. The intermediate insulating layer 604 ismade of a material which is different from the material of the cap layer620 and the side walls 622. The intermediate insulating layer 604 ismade of silicon oxide in this embodiment. (Step S177)

[0110] The first contact holes 606 a are formed using a SAC process. Theintermediate insulating layer 604 is etched using an etchant which has asmaller etching rate for SiN than for silicon-oxide. Therefore, the SiNsidewalls are used as a stopper. The intermediate layer 604 and thesilicon oxide 624 over the source region and drain region are etched inthis step. Subsequent steps are the same as those of the otherembodiments. (Step S178)

[0111] In this embodiment, high temperature formation of the first SiNsidewalls reduces the hydrogen and nitrogen that diffuses into thesilicon substrate 602 and the first SiN layers, which are formed at hightemperature, prevent hydrogen and nitrogen in the second sidewalls fromdiffusing into the silicon substrate 102. Therefore, interface traps,which are related to hot carrier, are reduced near the surface of thesemiconductor substrate, and the reliability of the MOSFET is improved.

[0112]FIG. 19 is a schematic diagram of this embodiment. As shown inFIG. 19, The impurity concentration of the LDD of this embodimentregions is different from that of the prior art. The LDD portion 712 aof this embodiment has a shallow portion 712 a 1 near the surface of thesemiconductor substrate, and the deep portion 712 a 2 formed under theshallow portion 712 a 1. The LDD portion 714 a of this embodiment has ashallow portion 714 a 1 near the surface of the semiconductor substrate,and the deep portion 714 a 2 formed under the shallow portion 714 a 1.

[0113]FIG. 22 shows the impurity concentration of the LDD regions ofthis embodiment. In FIG. 22, the dotted line shows an impurityconcentration of the prior art. As shown in FIG. 22, the peak of theimpurity concentration of this embodiment is deeper than that of theprior art. This peak is made in the deep portion 712 a 2 and 714 a 2.The depth of these deep portions are about 0.1 μm from the surface ofthe silicon substrate.

[0114] The hot carrier generation region is deeper than that of theprior art, because the peak of the impurity concentration is formed in adeeper portion of the substrate.

[0115]FIG. 20 is a flow chart of the method for manufacturing thesemiconductor device of this embodiment, and FIG. 21 is a crosssectional view showing the method for manufacturing the same. The methodfor manufacturing the semiconductor device of this invention isdescribed below.

[0116] The gate oxide layer 724 is formed on the surface of thesemiconductor substrate 702 by using thermal oxidation. This gate oxidelayer 724 has a thickness of about 10 nm.(Step S201)

[0117] The gate electrode material 716 and the cap layer material 720are formed on the gate oxide layer 724. A lithography method and ananisotropic etching technique, such as a RIE method, are employed toetch the gate electrode material 616 and the cap layer material 720. Thegate electrode 616 and the cap layer are thereby formed. (Step S202)

[0118] A first ion implantation for forming the shallow portion 712 a 1and 714 a 1 of LDD regions is performed using the cap layer 720 as amask. This implantation is performed at an acceleration voltage of 20keV. (FIG. 21(a), Step S203)

[0119] Then, a second ion implantation for forming the deep portion 712a 2 and 714 a 2 of LDD regions is performed using the cap layer 720 as amask. This implantation is performed at an acceleration voltage of 70keV. (Step S204)

[0120] A SiN sidewall layer, having a thickness of from 100 nm to 200nm, is formed on the semiconductor substrate using LP-CVD.

[0121] An anisotropic etching technique, such as a RIE method, isemployed to etch the SiN sidewall layer, so that SiN sidewalls 722 areformed. (Step S205)

[0122] Ion implantation for forming the source region 712 and drainregion 714 is performed by using the cap layer 720 and sidewalls 722 asa mask. An annealing is performed after the ion implantation. Thisannealing diffuses implanted ions and forms source region 712 and drainregion 714. (Step S206)

[0123] The intermediate insulating layer 704 is formed on semiconductorsubstrate 702. The intermediate insulating layer 704 is made of amaterial which is different from the material of the cap layer 720 andthe side walls 722. The intermediate insulating layer 704 is made ofsilicon oxide in this embodiment. (Step S207)

[0124] The first contact holes 706 a are formed using a SAC process. Theintermediate insulating layer 704 is etched using an etchant which hassmaller etching rate for SiN than than for silicon-oxide. Therefore, theSiN sidewalls are used as a stopper. The intermediate layer 704 and thesilicon oxide 724 located over the source region and drain region areetched in this step. Subsequent steps are the same as those of otherembodiments.

[0125] The hot carrier region is made deeper in this embodiment.Therefore, the trapping of hot carriers near the surface of thesemiconductor substrate is decreased, and the reliability of the MOSFETis improved.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; a silicon oxide layer formed over a surface ofsaid semiconductor substrate; a gate electrode formed over a firstportion of said silicon oxide layer; and a side wall structure formedover a second portion of said silicon oxide layer and adjacent said gateelectrode, wherein a thickness of said second portion of said siliconoxide layer is greater than a thickness of said first portion of saidsilicon oxide layer.
 2. A semiconductor device as claimed in claim. 1,wherein the thickness of said second portion of said silicon oxide layeris at least twice the thickness of said first portion of said siliconoxide layer.
 3. A semiconductor device as claimed in claim. 1, whereinthe thickness of said second portion of said silicon oxide layer is atleast 50% greater than the thickness of said first portion of saidsilicon oxide layer.
 4. A semiconductor device comprising: asemiconductor substrate; a gate oxide layer formed over saidsemiconductor substrate; a gate electrode formed over a first portion ofsaid gate oxide layer; a side wall structure formed adjacent said gateelectrode; and a diffusion deterrent layer formed between said side wallstructure and said semiconductor substrate; wherein a thickness of saiddiffusion deterrent layer is greater than a thickness of said firstportion of said gate oxide layer.
 5. A method for manufacturing asemiconductor device, comprising: forming a gate oxide layer on asurface of a semiconductor substrate; forming a gate electrode and overa first portion of said gate oxide layer; forming a cap layer over saidgate electrode; expanding a thickness of a second portion of said gateoxide layer other than said first portion located under said gateelectrode; forming a side wall structure on said second portion of saidgate oxide layer and adjacent said gate electrode; forming intermediateinsulating layer over said cap layer and said side wall structure; andforming a contact hole in said intermediate insulating layer using aSelf Aligned Contact process.
 6. A method for manufacturing asemiconductor device as claimed in claim. 5, wherein the thickness ofsaid second portion of said silicon oxide layer is at least twice thethickness of said first portion of said silicon oxide layer.
 7. A methodfor manufacturing a semiconductor device as claimed in claim. 5, whereinthe thickness of said second portion of said silicon oxide layer is atleast 50% greater than the thickness of said first portion of saidsilicon oxide layer.
 8. A method for manufacturing a semiconductordevice as claimed in claim. 5, wherein the thickness of said secondportion of said gate oxide layer is expanded using CVD.
 9. A method formanufacturing a semiconductor device as claimed in claim. 6, wherein thethickness of said second portion of said gate oxide layer is expandedusing CVD.
 10. A method for manufacturing a semiconductor device asclaimed in claim. 7, wherein the thickness of said second portion ofsaid gate oxide layer is expanded using CVD.
 11. A method formanufacturing a semiconductor device as claimed in claim.5, wherein thethickness of said second portion of said gate oxide layer is expandedusing thermal oxidation.
 12. A method for manufacturing a semiconductordevice as claimed in claim.6, wherein the thickness of said secondportion of said gate oxide layer is expanded using thermal oxidation.13. A method for manufacturing a semiconductor device as claimed inclaim.7, wherein the thickness of said second portion of said gate oxidelayer is expanded using thermal oxidation.
 14. A method formanufacturing a semiconductor device, comprising: forming a gate oxidelayer on a surface of a semiconductor substrate; forming a gateelectrode over a first portion of said gate oxide layer; forming a caplayer over said gate electrode; forming a side wall structure over asecond portion of said gate oxide layer and adjacent said gateelectrode; expanding the thickness of said second portion of said gateoxide layer located under said side wall structure using thermaloxidation; forming intermediate insulating layer over said cap layer andsaid side wall structure; forming a contact hole in said intermediateinsulating layer using a Self Aligned Contact process.
 15. A method formanufacturing a semiconductor device as claimed in claim. 14, whereinsaid expanding the thickness of said second portion of said gate oxidelayer is performed after formation of said intermediate insulatinglayer.
 16. A method for manufacturing a semiconductor device,comprising: forming a gate oxide layer on the surface of a semiconductorsubstrate; forming a gate electrode over a first portion of said gateoxide layer; forming a cap layer over said gate electrode; forming aside wall structure on a second portion of said gate oxide layer andadjacent said gate electrode; forming intermediate insulating layer oversaid cap layer and said side wall structure; and forming a contact holein said intermediate insulating layer using a Self Aligned Contactprocess; wherein the side wall structure is formed by CVD at thetemperature exceeding 850° C.
 17. A method for manufacturing asemiconductor device, comprising: forming a gate oxide layer on thesurface of a semiconductor substrate; forming a gate electrode over afirst portion of said gate oxide layer; forming a cap layer over saidgate electrode; forming a first portion of side wall structure over asecond portion of said gate oxide layer and adjacent said gateelectrode; forming a second portion of side wall structure over a secondportion of said gate oxide layer and adjacent said gate electrode;forming intermediate insulating layer over said cap layer and said sidewall structure; and forming a contact hole in said intermediateinsulating layer using a Self Aligned Contact process; wherein saidfirst portion of side wall structure is formed by CVD at the temperatureexceeding 850° C.
 18. A method for manufacturing a semiconductor device,comprising: forming a gate oxide layer on a surface of a semiconductorsubstrate; forming a gate electrode over a first portion of said gateoxide layer; forming a cap layer over said gate electrode; conducting afirst ion implantation step to form a the shallow portion of an LDDregion using said cap layer as a mask; conducting a second ionimplantation to form a deep portion of the LDD region using said caplayer as a mask; forming a side wall structure on a second portion ofsaid gate oxide layer and adjacent said gate electrode; formingintermediate insulating layer on said semiconductor substrate; andforming a contact hole in said intermediate insulating layer using aSelf Aligned Contact process.